1. Field of the Invention
The present invention relates to a semiconductor device having an insulation gate type field effect transistor of high breakdown voltage, and a method of fabricating such a semiconductor device.
2. Description of the Background Art
A semiconductor device having a MOS (Metal Oxide Semiconductor) transistor of high breakdown voltage will first be described as a conventional insulation gate type field effect transistor of high breakdown voltage.
FIG. 8 is a sectional view schematically showing a structure of a semiconductor device having a conventional MOS transistor of high breakdown voltage. Referring to FIG. 8, an n.sup.- well region 102 is formed at a surface of a p type substrate 1. A MOS transistor 10 of high breakdown voltage is formed at the surface of silicon substrate 1 in n.sup.- well region 102.
High breakdown voltage MOS transistor 10 includes a drain region 3, a source region 4, a gate insulation layer (silicon oxide film) 5, and a gate electrode layer 6. Drain region 3 and source region 4 are formed at the surface of n.sup.- well region 102 with a distance therebetween. Gate electrode layer 6 is formed on the region sandwiched by drain region 3 and source region 4 with gate insulation layer 5 thereunder.
Drain region 3 includes a p.sup.++ region 3a, a p.sup.+ region 3b in contact with p.sup.++ region 3a at the side of source region 4, and a p.sup.+ region 3c in contact with p.sup.++ region 3a at the side opposite to source region 4. This p.sup.++ region 3a has an impurity concentration substantially equal to that of source region 4. P.sup.+ regions 3b and 3c have an impurity concentration lower than that of source region 4.
A field insulation layer 7 is formed on p.sup.+ region 3b. The end portion of gate electrode layer 6 extends upon field insulation layer 7. Field insulating layer 7 is formed to enclose the circumference of high breakdown voltage MOS transistor 10 to electrically isolate MOS transistor 10 from other elements.
In this conventional structure, n.sup.- well region 102 has a P (phosphorous) impurity concentration distribution as shown in FIG. 9. Referring to FIG. 9, the P (phosphorous) impurity concentration is highest at the surface of the substrate, i.e., 2.times.10.sup.16 (atoms/cm.sup.3). The impurity concentration becomes lower as a function of depth into the substrate. The P (phosphorous) impurity concentration becomes equal to the B (Boron) concentration (1.0.times.10.sup.15 (atoms/cm.sup.3)) of a 10 (.OMEGA..cndot.cm) p type silicon substrate, whereby a pn junction is formed at the depth of approximately 5 .mu.m.
A method of fabricating a semiconductor device having a conventional MOS transistor of high breakdown voltage will be described hereinafter.
FIGS. 10-12 are sectional views of such a semiconductor device corresponding to sequential steps of a fabrication method thereof. Referring to FIG. 10, a silicon oxide film 11, for example, is formed on p type silicon substrate 1. A resist pattern 12 of a predetermined configuration is formed on silicon oxide film 11 by a conventional photolithographic technique. Using this resist pattern 12 as a mask, P (phosphorous) ions are implanted under the condition of 150 (keV) and 5.0.times.10.sup.12 (cm.sup.-2). Following removal of resist pattern 12, a heat treatment is applied at 1200.degree. C. for 360 minutes to diffuse and activate the impurities. Then, silicon oxide film 11 is removed.
Referring to FIG. 11, n.sup.- well region 102 having the impurity concentration peak in the proximity of the surface is formed at the surface of p type silicon substrate 1 by the above heat treatment.
Referring to FIG. 12, field insulation layer 7, and p.sup.+ regions 3b and 3c under field insulation layer 7, are formed at the surface of p type silicon substrate 1.
Then, following formation of gate insulation layer 5 and gate electrode layer 6 shown in FIG. 8, p.sup.+ regions 3a and 4 are formed by ion implantation. Thus, a MOS transistor 10 of high breakdown voltage is formed at the surface of n.sup.- well region 102.
Such a high breakdown voltage MOS transistor 10 is used for the driver of a fluorescent character display tube, for example. Recently, the demand for a clearer display is great. The need arises for a driver MOS transistor 10 of higher breakdown voltage.
However, the problem is that it is difficult to improve the breakdown voltage of MOS transistor 10 according to the impurity concentration distribution of the conventional n.sup.- well region 102. This will be described in details hereinafter.
FIGS. 13 and 14 show the spread of a depletion layer generated when a high voltage is applied across the drain of a conventional high breakdown voltage MOS transistor.
Referring to FIG. 13, application of -V to p.sup.++ region 3a under the state where source region 4, gate electrode layer 6, and p type silicon substrate 1 are at the ground potential causes the spread of depletion layer 120 from the pn junction between the drain region and n.sup.- well region 102. As this -V is increased, depletion layer 120 mainly spreads towards the deeper side of the substrate as shown in FIG. 14 to reach the pn junction between n.sup.- well region 102 and p type silicon substrate 1. As a result, punch through will occur between the drain region and p type silicon substrate 1. In the conventional case, it was difficult to improve the breakdown voltage since punch through easily occurs when a high voltage is applied across the drain region.
As shown in FIG. 9, n.sup.- well region 102 has an impurity concentration peak in the proximity of the substrate surface. Therefore, the impurity concentration gradient at the end portion of drain region 3 in FIG. 8 becomes steeper to result in higher electric field intensity. The breakdown voltage corresponding to avalanche breakdown could not be improved.